Outils, technologies

Articles scientifiques

Q. Huppert, T. Evenblij, M. Perumkunnil, F. Catthoor, L. Torres, and D. Novo. "Memory Hierarchy Calibration Based on Real Hardware In-order Cores for Accurate Simulation." In Proceedings of Design, Automation & Test in Europe Conference & Exhibition (DATE) 2021. https://hal-lirmm.ccsd.cnrs.fr/lirmm-03084343/document

-  ⇤ ← Revision 1 as of 2020-02-12 16:31:29 → 
  Size: 328
  Editor: danger@telecom-paristech.fr
  Comment:
+   ← Revision 5 as of 2021-03-04 10:08:25 → ⇥
  Size: 775
  Editor: David Novo
  Comment: Added reference on gem5 calibration of a Cortex A53 CPU
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+'''Page des publications utiles pour ARCHISEC'''
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-http://gem5.org/wiki/images/0/0e/ASPLOS2017 gem5 tutorial.pdf. 2017.
http://gem5.org/Supported Architectures. 2018.
https://www.qemu.org/. 2018.
https://www.linaro.org/blog/arm-trustzone-qemu/. 2018.
ARM, Cortex A9 MPCore Accelerator Coherency Port. Accessed: 2017-04-12. ARM
+= Outils, technologies =

 * http://gem5.org/wiki/images/0/0e/ASPLOS2017 gem5 tutorial.pdf. 2017.
 * http://gem5.org/Supported Architectures. 2018.
 * https://www.qemu.org/. 2018.
 * https://www.linaro.org/blog/arm-trustzone-qemu/. 2018.
 * ARM, Cortex A9 MPCore Accelerator Coherency Port. Accessed: 2017-04-12. ARM

= Articles scientifiques =

 * Q. Huppert, T. Evenblij, M. Perumkunnil, F. Catthoor, L. Torres, and D. Novo. "Memory Hierarchy Calibration Based on Real Hardware In-order Cores for Accurate Simulation." In Proceedings of Design, Automation & Test in Europe Conference & Exhibition (DATE) 2021. https://hal-lirmm.ccsd.cnrs.fr/lirmm-03084343/document