Welcome to the ARCHISEC project website !

ARCHISEC is a collaborative research project composed of five partners and coordinated by ANR

ARCHISEC main goal

ARCHISEC stands for "micro-ARCHItectural SECurity". The "microarchitecture" is an implementation of a processor to run an Instruction Set Architecture (ISA). It embeds architectural tricks to increase the performance level or reduce the consumption. For instance, the use of a cache memory optimizes the computation speed but can be the source of attacks exploiting the time difference between the state "hit" and "miss". The goal of ARCHISEC is to simulate the processor microarchitectures in order to find weaknesses, associated protections and anticipate future potential attacks.

ARCHISEC Summary

Attacks exploiting micro-architectural vulnerabilities, such as Meltdown, Spectre, Rowhammer, etc., are on the rise. Modern day System on Chip ”SoC”s embed increasingly complex design features, such as branch prediction, Out-of-Order execution, cache coherency protocols, integrated GPUs/FPGAs, new non volatile memories. The security aspect of these new architectures and technologies remains under-studied. This project aims at modeling the architectural problems with a virtual platform based on gem5. It will be used for penetration testing, evaluate the performance cost of countermeasures, anticipate new attacks and propose protections. These latter are validated on platforms based on ARM and RISC-V processors. The major impact of this project will be through the creation of a community around our virtual platform. The project will be carried out in collaboration with the SME Secure-IC, which will give industrial insights to the project.