Locked History Actions

Diff for "Presentation"

Differences between revisions 5 and 6
Revision 5 as of 2020-02-12 09:58:26
Size: 919
Comment:
Revision 6 as of 2020-02-12 09:59:52
Size: 978
Comment:
Deletions are marked like this. Additions are marked like this.
Line 5: Line 5:
This project coordinated by [[http://www.agence-nationale-recherche.fr//|ANR]] is a collaborative This project coordinated by [[http://www.agence-nationale-recherche.fr//|ANR]] is a collaborative research project composed of five [[partners|partners]].

Welcome to the ARCHISEC project website !

This project coordinated by ANR is a collaborative research project composed of five partners.

logo_anr.png

What is ARCHISEC and its main goal ?

ARCHISEC stands for "micro-ARCHItectural SECurity". The "microarchitecture" is an implementation of a processor to run an Instruction Set Architecture (ISA). It embeds architectural tricks to increase the performance level or reduce the consumption. For instance, the use of a cache memory optimizes the computation speed but can be the source of attacks exploiting the time difference between the state "hit" and "miss". The goal of ARCHISEC is to simulate the processor microarchitectures in order to find weaknesses, associated protections and anticipate future potential attacks.

Summary