Locked History Actions

Diff for "Presentation"

Differences between revisions 3 and 7 (spanning 4 versions)
⇤ ← Revision 3 as of 2020-02-11 17:58:41 →
Size: 697
Editor: danger@telecom-paristech.fr
Comment:
← Revision 7 as of 2020-02-12 10:01:53 → ⇥
Size: 963
Editor: danger@telecom-paristech.fr
Comment:
Deletions are marked like this. Additions are marked like this.
Line 5: Line 5:
This project is coordinated by [[http://www.agence-nationale-recherche.fr//|ANR]]
ARCHISEC is a collaborative research project composed of five [[Partners|partners]] and coordinated by [[http://www.agence-nationale-recherche.fr//|ANR]]   
Line 10: Line 9:
== ARCHISEC main goal ==
ARCHISEC stands for "micro-ARCHItectural SECurity".
The "microarchitecture" is an implementation of a processor to run an Instruction Set Architecture (ISA).
It embeds architectural tricks to increase the performance level or reduce the consumption.
For instance, the use of a cache memory optimizes the computation speed but can be the source of attacks exploiting the time difference between the state "hit" and "miss".
The goal of ARCHISEC is to simulate the processor microarchitectures in order to find weaknesses, associated protections and anticipate future potential attacks.
Line 12: Line 17:
== What is ARCHISEC ? ==
ARCHISEC stands for "micro-ARCHItectural SECurity".
The "microarchitecture" is an implementation of a processor to run an Instruction Set Architecture (ISA).
It generally embeds architectural tricks to increase the performance level or reduce the consumption.
For instance the use of a cache memory is almost mandatory to optimize the computation speed.
But it creates security weaknesses as the

== Summary ==		 == ARCHISEC Summary ==

Welcome to the ARCHISEC project website !

ARCHISEC is a collaborative research project composed of five partners and coordinated by ANR

logo_anr.png

ARCHISEC main goal

ARCHISEC stands for "micro-ARCHItectural SECurity". The "microarchitecture" is an implementation of a processor to run an Instruction Set Architecture (ISA). It embeds architectural tricks to increase the performance level or reduce the consumption. For instance, the use of a cache memory optimizes the computation speed but can be the source of attacks exploiting the time difference between the state "hit" and "miss". The goal of ARCHISEC is to simulate the processor microarchitectures in order to find weaknesses, associated protections and anticipate future potential attacks.

ARCHISEC Summary

last edited 2020-02-12 10:08:09 by danger@telecom-paristech.fr