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| This project is coordinated by [[http://www.agence-nationale-recherche.fr//|ANR]] |
ARCHISEC is a collaborative research project composed of five [[Partners|partners]] and coordinated by [[http://www.agence-nationale-recherche.fr//|ANR]] |
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| == ARCHISEC main goal == ARCHISEC stands for "micro-ARCHItectural SECurity". The "microarchitecture" is an implementation of a processor to run an Instruction Set Architecture (ISA). It embeds architectural tricks to increase the performance level or reduce the consumption. For instance, the use of a cache memory optimizes the computation speed but can be the source of attacks exploiting the time difference between the state "hit" and "miss". The goal of ARCHISEC is to simulate the processor microarchitectures in order to find weaknesses, associated protections and anticipate future potential attacks. |
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| == What is ARCHISEC ? == ARCHISEC stands for . == Summary == |
== ARCHISEC Summary == |
Welcome to the ARCHISEC project website !
ARCHISEC is a collaborative research project composed of five partners and coordinated by ANR
ARCHISEC main goal
ARCHISEC stands for "micro-ARCHItectural SECurity". The "microarchitecture" is an implementation of a processor to run an Instruction Set Architecture (ISA). It embeds architectural tricks to increase the performance level or reduce the consumption. For instance, the use of a cache memory optimizes the computation speed but can be the source of attacks exploiting the time difference between the state "hit" and "miss". The goal of ARCHISEC is to simulate the processor microarchitectures in order to find weaknesses, associated protections and anticipate future potential attacks.
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